1. Field of the Invention
The present invention relates generally to lithography manufacturing systems and, more particularly, to an optical metrology tool and system for monitoring of bias in lithographic and etch processes used in microelectronics manufacturing which is particularly useful for monitoring pattern features with dimensions on the order of less than 0.5 micron.
2. Description of Related Art
Lithography has a broad range of industrial applications, including the manufacture of semiconductors, flat-panel displays, micromachines, and disk heads. The lithographic process allows for a mask or reticle pattern to be transferred via spatially modulated light (the aerial image) to a photoresist film on a substrate. Those segments of the absorbed aerial image, whose energy exceeds a threshold energy of chemical bonds in the photo-active component (PAC) of the photoresist material, create a latent image in the photoresist. In some photoresist systems the latent image is formed directly by the PAC. In others (so-called acid catalyzed photoresists), the photo-chemical interaction first generates acids which react with other photoresist components during a post-exposure bake to form the latent image. In either case, the latent image marks the volume of photoresist material that either is removed during the development process (in the case of positive photoresist) or remains after development (in the case of negative photoresist) to create a three-dimensional pattern in the photoresist film.
The principal determinant of the photoresist image is the surface on which the exposure energy equals the photoresist threshold energy in the photoresist film. Exposure and focus are the variables that control the shape of this surface. Exposure, set by the illumination time and intensity, determines the average energy of the aerial image per unit area. Local variations in exposure can be caused by variations in substrate reflectivity and topography. Focus, set by the position of the photoresist film relative to the focal plane of the imaging system, determines the decrease in modulation relative to the in-focus image. Local variations in focus can be caused by variations in substrate film thickness and topography.
Generally, because of the variations in exposure and focus, patterns developed by lithographic processes must be continually monitored or measured to determine if the dimensions of the patterns are within acceptable range. The importance of such monitoring increases considerably as the resolution limit, which is usually defined as minimum features size resolvable, of the lithographic process is approached. The patterns being developed in semiconductor technology are generally in the shape of lines both straight and with bends, having a length dimension equal to and multiple times the width dimension. The width dimension, which by definition is the smaller dimension, is of the order of 0.1 micron to greater than 1 micron in the current leading semiconductor technology. Because the width dimension is the minimum dimension of the patterns, it is the width dimension that challenges the resolution limits of the lithographic process. In this regard, because width is the minimum and most challenging dimension to develop, it is the width dimension that is conventionally monitored to assess performance of the lithographic process. The term "bias" is used to describe the change in a dimension of a feature from its nominal value. Usually the bias of interest is the change in the smallest of the dimensions of a given feature. Further, the term "bias" is invariably used in conjunction with a process such as resist imaging, etching, developing etc. and described by terms such as image bias, etch bias, print bias etc.
Monitoring of pattern features and measurement of its dimensions (metrology) is typically performed using either a scanning electron microscope (SEM) or an optical tool. Current practice in the semiconductor industry is to use topdown SEMs for the in-line metrology of all critical dimensions below approximately 0.7 um. SEM metrology has very high resolving power and is capable of resolving features of the order of 0.1 micron. The SEM measurement is an interpretation of an average intensity profile over a user-defined segment of the topdown image. Unfortunately, SEM metrology is expensive to implement, relatively slow in operation and difficult to automate. The need to reconstruct the three-dimensional pattern on the wafer from its two-dimensional image over the range of conditions encountered in semiconductor processing precludes the accuracy of topdown measurement. In-line measurement of critical dimension (CD) below 0.5 um must currently be made on SEM tools for the control of the lithography and etch sectors. At best, algorithms that attempt to determine the absolute dimensions at a fixed pattern height (e.g., the interface of the pattern with the underlying substrate), are accurate to only 30-50 nm--a substantial fraction, if not all, of current critical dimension tolerance. Thus, to achieve the necessary dimensional control of current and future semiconductor products, topdown SEMs require correlation to methods deemed more accurate, such as, cross-section SEMs, TEMs (transmission electron microscopes) and AFMs (atomic force microscopes). Between such "calibrations", current topdown SEMs are believed to sustain measurement precision on the order of 10 nm (3.sigma.). The extendibility of topdown SEMs to the CD metrology required of future generations of chips is in question. The need to measure individual features below 0.25 um poses a serious challenge not just to their imaging capability, but to all the subsystems required for automated measurement--pattern recognition, gate placement, edge detection, and the like. Even with major improvements in automation, topdown SEMs remain slow and expensive compared to the optical tools used in overlay metrology. Some proposed alternatives, such as the AFM, are likely to be slower and more expensive.
The CD metrology dilemma, summarized above, portends a separation of roles for in-line and off-line metrology in which the "accuracy" of in-line metrology is sacrificed for precision, sensitivity and speed. The principal role of in-line tools will be to maintain the process at predetermined operating points known to correlate to high yield. The in-line metrology will also be able to generate much of the routine process characterization data (e.g., focus-exposure matrices, process window comparisons, swing curves, and the like) where there is a good understanding of the underlying physical effects. The role of off-line metrology tools will be to keep the in-line tools calibrated (maintain correlation to physical attributes of the pattern) and to enable deeper characterization and diagnosis of the patterning process.
The attributes required of in-line metrology tools are sensitivity to process variation, precision, stability, matching, ease of calibration, speed, low cost of ownership and, of course, that they be nondestructive. Optical tools will re-emerge to fulfill this role for CD metrology. The principal attributes required of off-line metrology/inspection tools are a combination of the ability to "see" the chip pattern with precision and accuracy. The topdown SEM is likely to return to an off-line mission where, along with cross-section SEM, TEM, AFM, electrical probe, etc., it will continue to serve an important role. In semiconductor manufacturing, both in-line and off-line metrology remain subservient to the ultimate arbiter--electrical chip performance.
Although optical metrology overcomes the above drawbacks associated with SEM and AFM metrology, optical metrology systems are unable to resolve adequately for measurement of feature dimensions of less than about 1 micron. Additionally, false sensitivity has limited the applicability of optical microscopy to sub-micron metrology on semiconductor product wafers.
The degradation of optical resolution as chip dimensions approach the wavelength of light precludes the application of optical microscopy to the measurement of individual chip features. Even setting aside the accuracy requirement for in-line metrology, the blurred images of adjacent edges overlap and interfere, and the behavior of the intensity profile of the image no longer bears any consistent relationship to the actual feature on the wafer. It is this loss of measurement "consistency" (definable as a combination of precision and sensitivity) that establishes the practical limit of conventional optical metrology in the range of 0.5-1.0 um.
With regard to false sensitivity, the thin films used in semiconductor manufacturing vary widely in their optical characteristics. Optical metrology is susceptible to variations in the thickness, index of refraction, granularity and uniformity of both the patterned layer and underlying layers. Film variations that affect the optical image can be falsely interpreted as variations in the pattern dimension.
Improvements in monitoring bias in lithographic and etch processes used in microelectronics manufacturing have been disclosed in U.S. patent application Ser. Nos. 08/359,797, 08/560,720 and 08/560,851. In Ser. No. 08/560,851, a method of monitoring features on a target using an image shortening phenomenon was disclosed. In Ser. No. 08/560,720, targets and measurement methods using verniers were disclosed to measure bias and overlay error. In these applications, the targets comprised arrays of spaced, parallel elements having a length and a width, with the ends of the elements forming the edges of the array. While the targets and measurement methods of these applications are exceedingly useful, they rely on the increased sensitivity to process variation provided by image shortening.
Accordingly, there is still a need for a method of monitoring pattern features of arbitrary shape with dimensions on the order of less than 0.5 micron, and which is inexpensive to implement, fast in operation and simple to automate. There is a need for a process for determining bias which enables in-line lithography/etch control using optical metrology, and wherein SEM and/or AFM metrology is required only for calibration purposes.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an optical metrology tool and apparatus for determining bias and overlay error in patterns deposited as a result of lithographic processes.
It is another object of the present invention to provide a method and target for determining bias and overlay error in patterns deposited as a result of lithographic processes.
It is a further object of the present invention to provide a method and target which combines measurement of bias and overlay error in deposited patterns, and which utilize little space on a wafer substrate.
It is yet another object of the present invention to provide bias and edge overlay targets which are readable by optical microscopy.
It is a further object of the present invention to provide a process for measuring bias using targets which are intentionally not resolved by the metrology tool employed.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.